1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Prior Art
In recent years, the speed of micro processing units built into electronic products such as communication devices and home electric appliances has been increased and they have been sophisticated. Accordingly it is demanded that a DRAM (Dynamic Random Access Memory) as a semiconductor device provides higher integration or higher capacity.
The memory cell is getting smaller and smaller to achieve LSI (Large Scale Integration) having a high-capacity DRAM. However, the electric charge of a capacitor used for a memory cell needs to be at least 30 to 50 fF (femtofarad: 10−15 F). The problem is how to form a high-capacity capacitor on a small chip. The problem can be solved by, for example, increasing the surface area of a capacitor, reducing the thickness of the insulator of a capacitor, or increasing dielectric constant of the insulator of a capacitor.
Applying those methods mentioned above, there have been utilized a stack cell (a cell whose surface area is raised by a coil type capacitor), a trench cell (a cell whose surface area is raised by a deep trench), a HSG (Hemi-Spherical Grain) cell (a cell whose surface area is raised by depositing hemispherical silicon grains on a surface), a RSTC (Reversed Stacked Capacitor) cell (a cell whose surface area is raised by a glass type capacitor). Besides, development research is being made concerning a STO film and a PZT film having high dielectric constant.
For example, the applicant of this invention manufactured 256 M bit DRAM in which 570 million devices are integrated on a silicon chip sized 13.6×24.5 mm by 0.25 μm CMOS (Complementary Metal-Oxide Semiconductor) process. Its memory cell has an area of around 0.72 μm2.
FIG. 1(a) is a cross-section diagram showing a trench cell used for a DRAM as a conventional semiconductor device. FIG. 1(b) is a pattern diagram showing an appearance of crown type cylinders of the trench cell shown in FIG. 1(a).
In FIG. 1(a), broken line 120 indicates an insulating film of a capacitor called crown type cylinder.
A photomask is necessary in order to produce these crown type cylinders by photolithography. On the photomask, a plurality of cylinder patterns as mask patterns are formed at specified intervals.
FIG. 2 is a plan view showing an example of a conventional photomask used for the manufacture of a semiconductor device. FIG. 3 is a plan view showing another example of a conventional photomask used for the manufacture of a semiconductor device.
FIG. 2 shows a 6 F2 ½ pitch cell type photomask on which rectangular cylinder patterns are formed. FIG. 3 shows a 8 F2 ¼ pitch cell type photomask on which rectangular cylinder patterns, having reentrant angles at a pair of opposite corners of each rectangle, are formed. In FIGS. 2 and 3, resist form images have a long elliptic shape (according to the result of optical simulation).
There will be described these pitches of the cylinder patterns, 6 F2 ½ pitch and 8 F2¼ pitch.
F is equivalent to ½ of the pitch of word lines positioned in a memory cell of a DRAM. In the memory cell, a cell having a structure in which the minimum cell units are repeated within the area of 2 F×3 F or 2 F×4 F is called “6 F2 cell” or “8 F2 cell”, respectively. Regarding the pitch, provided that the distance between adjacent bit contacts connected with one bitline is 1 pitch, a cell having a structure in which device areas adjacent in the direction parallel to a bitline are offset with respect to one another by ½ pitch or ¼ pitch is called “½ pitch cell” or “¼ pitch cell”, respectively.
The conventional 8 F2¼ pitch and 6 F2½ pitch DRAM cells have cylinder patterns of elliptic aperture with slenderness ratios in the range of 1.2 to 2.0 (the aperture form of a capacitor of a DRAM), which are densely disposed. In the above mentioned cylinder pattern, in order to ensure the maximum capacitance of a capacitor, a transcription exposure condition that can create the maximum area of each aperture is employed.
In order to maximize the lateral area of each aperture for forming a storage capacitor film, the resist pattern mentioned above is used as an etch mask, and high-aspect deep apertures are fabricated. For example, such techniques are described in Japanese Patent Application laid open No. HEI 10-242417 and also in “Nikkei Microdevices Vol. 11” pp. 86-87, Nikkei Business Publications. Inc., Nov. 1, 2003.
Incidentally, because of the minimization of design with high-integration, cylinder patterns can occupy smaller area, and apertures cannot be enlarged. As a result, the enough peripheral length of an aperture cannot be attained, which causes the difficulty of ensuring an desired capacitance.
Besides, when forming a high-aspect microscopic crown structure, a surface tension arisen during wafer surface finishing by wet chemical processing acts as stress to the side of a cylinder. Therefore, the patterns will be broken as shown in FIG. 1(b).
To increase the capacitance of a cylinder type capacitor of the current laminated structure by utilizing existing dielectric materials and electrodes, there is no other way than to enlarge the peripheral length of the cylinder aperture and further deepen the cylinder depth as compared to those of an existing cylinder.
However, because the aperture of an existing cylinder has a long elliptic shape as shown in FIGS. 2 and 3, there is obviously no other choice than to enlarge the aperture area to increase the peripheral length of the aperture.
Also, when the aperture area is enlarged with a fixed pitch, it is difficult to achieve an agreeable resist form because the width between adjacent patterns becomes considerably narrow. Under such circumstances, it becomes difficult to etch while leaving enough margins between adjacent aperture patterns.
Furthermore, as the sidewall of a cylinder has a very high and thin film structure with aspect 10, which causes degradation in mechanical strength to the stress against the side of the cylinder.